In many electronic systems, the clock signals that drive an integrated circuit are generated by a phase-locked loop (PLL) frequency synthesizer. The performance of the PLL frequency synthesizer is dependent on several parameters, including a minimum charge pump pulse width and corresponding phase noise. The minimum charge pump pulse width is limited by a feedback signal propagation time, which is the amount of time for a feedback signal from the charge pump to reset the phase detector and to propagate back through to the charge pump. The corresponding phase noise may not be reduced beyond the limits of the minimum charge pump pulse width.
In addition, some currently available PLL frequency synthesizers include one or more delay circuits to provide time-delayed phase signals in order to increase slew rates with respect to the charge pump output. In these PLL frequency synthesizers, therefore, the feedback signal propagation time is increased, resulting in an increased minimum charge pump pulse width and corresponding phase noise.